EDN

A Designer’s Guide to CMOS RF Models

In recent years we have begun to see references to “RF” CMOS processes and to “RF” models for those processes. This article will explore what the real meanings of such “RF” designations are, and what ...
EDN

A primer on negative-capacitance FET technology

It has been long known that complementary metal-oxide semiconductor (CMOS) transistors suffer from a scaling issue. As CMOS field-effect transistors (FETs) get smaller, they become less power ...
Design-Reuse

Fujitsu Laboratories Develops World's First CMOS-based Power Amplifier Operating at 77GHz

Tokyo, Japan -- Feb 4, 2008 -- Fujitsu Laboratories, Ltd. today announced the development of a millimeter-waveband power amplifier (PA) using standard 90nm CMOS process technology. Targeting ...
Design-Reuse

Metal layers a key to interconnect delay?

Interconnect delay has moved to the forefront as the limiting factor in IC performance, replacing a longtime concern with switching speeds. That concern was prompted by advancements in deep-submicron ...
Electronic Design

3D NAND Hits 176 Layers

Micron Technology recently unveiled 176-layer, triple-level-cell (TLC), 3D NAND flash memory with a 30% smaller die size that employs a new replacement-gate (RG) NAND technology. The chips offer a 35% ...