EDN

Decreasing parasitic capacitance in IC layouts

As the Semiconductor industry is growing so does the density of devices on chip. With the increasing density and decreasing spacing rules, the most significant effect that takes birth is parasitic.
Semiconductor Engineering

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even ...
Electronic Design

Use Analog Techniques To Measure Capacitance In Capacitive Sensors

Capacitive sensors are found in a wide range of equipment, from consumer electronics to industrial/process control. Touch buttons are increasingly found in lamps and dimmers. Motion detectors can ...
EDN

Basics of Bench Silicon Validation – PCB Passives

Parasitic capacitance is unwanted capacitance created on PCB boards, and every PCB designer should watch out for it. Two closely spaced signal traces can create a lateral parasitic capacitance within ...
Semiconductor Engineering

Reducing BEOL Parasitic Capacitance Using Air Gaps

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced ...
Electronic Design

100V and 125V Tantalum Polymer SMD Capacitors

AVX Corporation is expanding its award-winning TCJ Series with two new high-voltage tantalum polymer chip capacitors. Rated for 100V and 125V - nearly twice the rated voltage of similar products ...