EDN

IP Economics for SOC Design from the Reuse Methodology Manual

This is my seventh blog entry discussing outdated elements of the 3 rd edition of the Reuse Methodology Manual (the RMM) for SOC design, which first appeared in 1997. Here are some important ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
EDN

How to manage changing IP in an evolving SoC design

In a previous article, Getting started in structured assembly in complex SoC designs, an unexceptional system-on-chip (SoC) design was shown to contain hundreds of intellectual property (IP) blocks.
Nasdaq

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

Next-generation CXL VIP and System VIP tools provide faster path to testing and compliance with the latest standard SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) ...
Seeking Alpha

Arteris Interconnect IP Selected by VeriSilicon for High-Performance SoC Design

CAMPBELL, Calif., Sept. 10, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that VeriSilicon (688521.SH), ...
NBC News

HDL Design House Adopts Magma's Full Suite of Software to Accelerate SoC and IP Development

SAN JOSE, Calif., March 31, 2011 (GLOBE NEWSWIRE) -- Magma Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, and HDL Design House, creators of re-usable IP cores, verification ...
Electronic Design

Advanced SoC Development Uses Next-Gen IP Integration Tools

The considerable growth of the number of logical cores in a chip increases the number of networks-on-chip (NoCs) per system-on-chip (SoC), fueling design complexity. Demand is on the rise for better ...
Electronic Design

Breaking Barriers in SoC Design with Smart NoC Automation

The evolution of semiconductor design has driven modern systems-on-chip (SoCs) to unprecedented levels of complexity. Today’s leading-edge SoCs often integrate hundreds of intellectual-property (IP) ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
Design And Reuse

TES offers CAN Flexible Data-Rate Controller IP Core for System-on-Chip (SoC) Designs

TES Electronic Solutions GmbH adds to its IP portfolio a new VHDL-based CAN Flexible Data-Rate (FD) controller IP core. The IP is designed for System-on-Chip (SoC) implementations and can be ...
Semiconductor Engineering

Why Silicon IP Has Become the Foundation of Modern SoC Design

Addressing challenges of using silicon IP, tracking IP cores, and taking advantage of the flexibility of modular design requires a proven process. It also requires a state-of-the-art IP management ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of the industry’s first Verification IP (VIP) and System-Level VIP (System VIP) for the ...