Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Vivek Yadav, an engineering manager from ...

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a “test re-use” strategy ...

For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability ...

One of the questions I often get from customers is “How should I design a board for the best signal integrity?” My expertise is in measurement signal integrity but there is one area where these two ...

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...

JTAG has its place but it is not by any means the total solution. Boundary scan, as standardized by IEEE 1149.1 and commonly referred to as JTAG, has truly revolutionized the testability of circuit ...

Whether you are a DFT engineer or a SoC designer, connectivity validation will no doubt be a top priority when taking steps to guarantee the functionality and reliability of your device. SoC designs ...

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a "test re-use" strategy ...