Abstract: This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline ...
Neal has more than 20 years of experience in financial and business journalism covering retail investing, airlines, pharmaceuticals, healthcare, sustainability, technology, and retail. He has worked ...
Abstract: This article presents a power- and area-efficient multistandard serial link transceiver designed for application rates of up to 112 Gb/s, such as OIF CEI-112G and IEEE 802.3ck 400GBASE. The ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback